The summary.
DESCRIBING HARDWARE IS NOT WRITING A PROGRAM
Everything described happens simultaneously. Code that simulates correctly but cannot be synthesised is the commonest newcomer error.
Separate synthesisable design from verification code strictly.
METASTABILITY AT CLOCK DOMAIN CROSSINGS CAUSES RARE, RANDOM, UNDIAGNOSABLE FAILURES
Use synchronisers and disciplined crossing, always.
VERIFICATION FREQUENTLY EXCEEDS DESIGN EFFORT
Because a manufactured chip cannot be patched, and a respin costs a great deal and months. Coverage is what answers whether verification is actually complete.
FPGA ITERATION IS FAR SLOWER THAN SOFTWARE ITERATION
Placement and routing can take hours, so verify thoroughly in simulation before building.
MOST DESIGNS SHOULD USE MATURE PROCESS NODES
They are far cheaper and entirely adequate. Advanced nodes carry vastly higher design and manufacturing cost.
YIELD DOMINATES SEMICONDUCTOR ECONOMICS
Defects are inevitable and larger chips are likelier to contain one, which is why partial defects are sold as lower-specification parts.
