Producing a custom chip.
WHAT THE STAGES ARE
Specification Design description Functional verification Synthesis into a gate-level design Placement of cells Routing of connections Timing, power and signal integrity analysis Physical verification against manufacturing rules
Tape-out: sending the design for manufacture
WHAT TAPE-OUT MEANS
The point after which changes require starting substantial parts again.
WHAT A MASK SET COSTS
A very large sum, rising sharply at smaller process nodes.
WHY THAT DRIVES EVERYTHING
The cost of being wrong is enormous, which is why verification dominates.
WHAT A PROCESS NODE IS
A manufacturing technology generation, named by a number that no longer corresponds to a physical dimension.
WHAT SMALLER NODES PROVIDE
More transistors, lower power per operation.
WHAT THEY COST
Vastly higher design and manufacturing cost.
WHAT MOST DESIGNS USE
Mature nodes, which are far cheaper and entirely adequate.
WHAT INTELLECTUAL PROPERTY BLOCKS ARE
Pre-designed components licensed for inclusion.
WHY THEY MATTER
Almost no chip is designed entirely from nothing.
WHAT TO PLAN
Long timelines, measured in years for complex chips.
